The first rule we had to follow was that, to Burroughs Corporate, we were a Data Comm. Processor (DCP). This was a stealth project, if Corporate in Detroit (or Pasadena) found out about it, we were sunk. The DCP was part of the IO subsystem, so we had to use Universal IO (UIO) subsystem components and logic. I would have preferred to build the B5900 out of ECL logic, but, as I described earlier, that would not be in the cards. ECL was a competitor to BCML, and no competition of that type was allowed. All logic used at Burroughs had to be qualified by the components group. They were responsible for making sure the logic was suitable for Burroughs, that it had multiple sources, and was available from approved vendors.

I used ECL for the Black Box at MIT and using it on the B5900 would have resulted in a processor that was about twice as fast as the final product we produced, for about 25% higher cost. A good tradeoff, but one what was not politically acceptable. We could use TTL, because that was what the IO group was using. TTL was approved by the corporation. The IO group had a standard logic card design and backplane design. While I would have preferred a different packaging scheme, there was no way for us to fund one. Erv told us we could design using UIO subsystem components, circuit boards, and backplanes, or forget the project. The circuits group and I were concerned if the design of the UIO (Universal IO) circuit boards and backplane could support a computer. UIO circuit boards were about 14”x12”, with a 194-pin backplane connector and four 48 pin frontplane connectors. The B5900 would be 14 boards, most UIO controllers were a single board, some were two or three. Most high speed data traffic was on the UIO boards themselves, we would be running several high speed data busses on the backplane between the 14 boards. These were unanswered questions, and were concerns, but we decided to proceed and deal with them later, which would cost us at the end of the project. Luckily by then we could afford the cost.

Next we had to write a detail design specification. The B5900 design was to be modular; the specification defined what each module did, and how it interfaced to the others. I partitioned the design into the Data Processor (DP) (which I designed), the Program Controller (PC) which Dave Matty designed, the Storage Level Controller (SLC) which Al Regalato designed, the Host Data Processor (HDP) which Cas Pencak designed, the Maintenance Processor (MP) which Dave Eaves designed, and the Memory Controller (MC) which Bob Olson and Greg Wright designed at Piscataway New Jersey. The modular design and bus structure, with many of the same designations, was retained in the future A3-A9 series Unisys E-mode mainframes.